[J2] Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction


Tolerating timing error due to power supply noise (PSN) in digital circuits can be done with adding voltage margins. Conservative addition of voltage margins leads wastes of power reducing the battery life in isnternet of things (IoT) devices. This paper aims to provide guidelines to avoid over-design due to PSN especially for the low cost IoT devices. To this end, we first present an accurate time-domain behavioral model of timing slack variation due to PSN accounting for the clock-data compensation (CDC). The accuracy of the model is verified against SPICE for complex designs including AES engine and LEON3 processor. To prove the effectiveness of our model for reducing voltage margin, we utilize our model in standard VLSI design flow for various examples such as timing slack vs. noise frequency analysis, determining optimal value of an on-die capacitor, analyzing the effects of time borrowing technique, and PVT variation simulations. The analysis shows that the model helps reduce pessimism in estimated timing slack by considering effects of CDC.

IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)