[C63] A Hybrid Precision Network with Efficient Processing Elements for 3D Hand Pose Estimation


This paper presents a hybrid precision network that combines binary and multi-bit layers for efficient 3D hand pose estimation on resource-constrained devices. By transforming the state-of-the-art HandFoldingNet (HFN) architecture, we significantly reduce memory usage and computational complexity while maintaining accuracy. Our design integrates specialized binary XNOR and multi-bit Processing Elements optimized for low-power and high efficiency. Implemented on FPGA, the hybrid processing elements units demonstrate up to 46% higher efficiency compared to traditional methods. This hybrid approach enables deploying advanced neural networks like HFN on mobile and edge devices for real-time applications.

International SoC Design Conference 2024